riscv

RISCV

May 31, 2020
riscv, cs, architecture, thesis

tags Computer Science Operating Systems Computer Architecture Understanding RISCV stack pointer # L06 RISCV Functions(6up).pdf # Exceptions # Exception are unusual condition occurring at run time associated with an instruction in the current RISCV thread. Exceptions may be converted to traps, but that all depends on the execution environment. Traps # Trap refers to the synchronous transfer control to a trap handler caused by an exceptional condition occurring within a RISC thread. ...

Understanding key concepts before writing a Kernel

May 3, 2020
blog, kernel
C, riscv

In this series of posts, I intend to document my re-go on writing a small, portable kernel for the RISC-V architecture. I developed a micro-kernel for the RISC-V ISA in my bachelor thesis, however, due to the time it takes on developing a kernel, and the time I had on writing a bachelor’s thesis, I choose on writing the kernel for the Sifive’s HiFive1 Rev B development board due to their well written bare metal compatibility Library for the board, low cost and most importantly, RISC-V. ...