RISC-V Instruction Format

RISC-V Instruction Format

August 13, 2021 | riscv

The base ISA has six instruction formats: (i) the R-format for register operations, (ii) I-format for immediate short and loads values, (iii) S-format for stores, (iv) B-format for conditional branches, (v) U-format for instructions with upper immediate, and (vi) J-format for unconditional jumps. Given that the ISA has six instruction formats, the simplification and decoding of instructions are much more straightforward compared to ARM or x86 architectures. RISC-V provides three register operands at the same position in all formats, simplifying the decoding process. In addition, the specified registers to be read or written are always in the same place in all instructions, enabling register access to start before the instruction decoding phase (Patterson and Waterman 2017; Waterman et al. 2014).

Bibliography #

Patterson, David, and Andrew Waterman. 2017. The RISC-V Reader: An Open Architecture Atlas. 1st ed. Strawberry Canyon.

Waterman, Andrew, Yunsup Lee, David A. Patterson, Krste Asanovic, Volume I User-level Isa, Andrew Waterman, Yunsup Lee, and David Patterson. 2014. “The RISC-V Instruction Set Manual.”

Go to random page