RISCV

RISCV

May 31, 2020
riscv, cs, architecture, thesis

tags
Computer Science Operating Systems Computer Architecture
Understanding

RISCV stack pointer #

L06 RISCV Functions(6up).pdf #

Exceptions #

Exception are unusual condition occurring at run time associated with an instruction in the current RISCV thread. Exceptions may be converted to traps, but that all depends on the execution environment.

Traps #

Trap refers to the synchronous transfer control to a trap handler caused by an exceptional condition occurring within a RISC thread. Trap handlers normally execute in a more privilege environment.

Interrupts #

Interrupt refers to an external event that occurs asynchronously to the current RISCV thread. When an interrupt occurs, some instruction gets selected to receive an interrupt exception and subsequently experiences a trap.

The Machine trap vector base-address register (mtvec) #

When something happens in RISCV, the CPU calls the function stored in mtvec. mtvec is a XLEN (32-64bit wide) read/write register that holds a trap vector configuration which consists of the base address (the function address) and the vector mode.

RISCV requires mtvec to be always implemented, but can contain a hardwired to a read-only value. The base field must always be aligned on a 4-byte boundary however, mode settings may impose additional base field alignment constraints.

We can visualize this as an array for XLEN bits:

/* xlen is 32-bits ie. (int32_t) or 64-bits ie. (int64_t) */
xlen mtvec[xlen];
xlen base = mtvec[xlen-2];
xlen mode = mtvec[2];

If mode gets set to DIRECT MODE, it means all traps will go to the exact same function, if VECTOR mode is set, all synchronous exceptions into machine mode cause the PC to be set to the address of the base field, whereas interrupts will set PC to base + 4 * cause. For example Table 1 has machine-mode timer interrupt code 7 causes the PC to be set to BASE + 0x1c (BASE + 4 * 7).

Interrupt1Exception codeReason
10User software interrupt
11Supervisor software interrupt
12Reserved
13Machine software interrupt
14User timer interrupt
15Supervisor timer interrupt
16Reserved
17Machine timer interrupt
18User external interrupt
19Supervisor external interrupt
110Reserved
111Machine external interrupt
1>= 12Reserved
00Instruction address misaligned
01Instruction access fault
02Illegal instruction
03Breakpoint
04Load address misaligned
05Load access fault
06Store/AMO address misaligned
07Store/AMO access fault
08Environment call from U-mode
09Environment call from S-mode
010Reserved
011Environment call from M-mode
012Instruction page fault
013Load page fault
014Reserved
015Store/AMO page fault
0>= 16Reserved

Privilege modes #

LevelEncodingNameAbbreviation
000User/ApplicationU
101SupervisorS
210Reserved
311MachineM

Provides protection between different components of the software stack #

Any attempts to perform an operation not allowed by the current mode will cause an exception to be raised #

These exceptions will normally cause traps into the underlying execution environment #

Machine mode #

Highest privilege #

Mandatory privilege level for RISC-V hardware platform #

Trusted code environment #

Low level access to the machine implementation #

Manage secure execution environments #

User mode and supervisor mode are indented for conventional application and operating systems #

Number of levelsSupported modesIndented Usage
1MSimple embedded systems
2M, USecure embedded systems
3M, S UUnix-like operating systems

Exceptions #

Any attempts to access non-existent CSR, read or write a read-only register raises an illegal instruction #

A read/write register might also contain bits that are read-only, in which writes to read-only bits are ignored #

Supervisor mode #

http://www-inst.eecs.berkeley.edu/~cs152/sp12/handouts/riscv-supervisor.pdf

Steps to reproduce the behavior #

Switch to machine mode (if not already by default) #


  1. 0 for asynchronous and 1 for synchronous ↩︎