November 21, 2020
tags Computer Architecture Operating Systems Translating virtual address space in RISCV in Sv39
Virtual address: 0x7d_beef_cafe Virtual address in binary: 0b0111_1101_1011_1110_1110_1111_1100_1010_1111_1110
VPN VPN VPN 12-bit offset 1_1111_0110 1_1111_0111 0_1111_1100 1010_1111_1110 502 503 252
November 16, 2020
tags RISCV Computer Architecture Notes on RISC-V CPU HARD IP Cores enter SoC FPGAs presentation
Frozen base ISA Consolidation in the semiconductor industry RISC-V is not owned by anyone Custom instruction extension to extend the virtuous cycle of semiconductor innovation PolarFire SoC - RISC-V enabled innocation platform # Mixed critically RTOS + Linux support Defence grade security Exceptional reliability Designed for low-power L2 memory subsystem Can be made to be deterministic Not all L2 are deterministic
June 21, 2020
tags Computer Architecture Computer Science Database
May 31, 2020
May 31, 2020
tags Computer Science Operating Systems Computer Architecture Understanding RISCV stack pointer # L06 RISCV Functions(6up).pdf # Exceptions # Exception are unusual condition occurring at run time associated with an instruction in the current RISCV thread. Exceptions may be converted to traps, but that all depends on the execution environment.
Traps # Trap refers to the synchronous transfer control to a trap handler caused by an exceptional condition occurring within a RISC thread.